Pascal · Pascal
AcceleratorsGPU0023
NVIDIA
Tesla P100 16GB SXM2
No tracked market supply yet. Kovara does not currently track public offerings for this accelerator.
Accelerator Overview
Core hardware and lifecycle, drawn from Kovara master data.
Core hardware
- Architecture
- Pascal
- Generation
- Pascal
- VRAM
- 16 GB
- Memory type
- HBM2
- Memory bandwidth
- 0.732 TB/s
- Form factor
- SXM2
Lifecycle / usage
- Primary use
- HPC / legacy AI training
- Launch year
- 2016
- Generation status
- Legacy
- Last verified
- 03 Sept 2026
The hardware in depth
What the recorded specifications mean in practice, and what this accelerator is used for.
Specs, explained
Used for HPC and legacy AI training
- VRAM
- 16 GB
- Memory type
- HBM2
- Memory bandwidth
- 0.732 TB/s
HBM (High Bandwidth Memory) is stacked in layers and sits right next to the processor on the same package. That short, wide path is what gives accelerators with HBM their memory bandwidth, so they are usually chosen for work limited by how fast data reaches the cores, such as large-model inference and HPC simulation.
VRAM is the working space on the card. Model weights, activations and datasets have to fit in it, or be split across several GPUs. Rule of thumb for the weights alone at 16-bit precision (about 2 GB per billion parameters): up to roughly 8 billion parameters, before activations and cache. This is arithmetic on the recorded VRAM, not a benchmark.
- Architecture
- Pascal
- Launch year
- 2016
- Lifecycle status
- Legacy
Pascal introduced NVLink to NVIDIA's data-center GPUs, first on the Tesla P100. (General context about the architecture, not a statement about this specific card.)
Launched in 2016. Kovara's records list it as a legacy part.
- NVLink
- Supported
- MIG
- Not supported
- Form factor
- SXM2
- TDP
- 300 W
NVLink is a direct GPU-to-GPU link. Where it is supported, GPUs in the same server can exchange data faster than over PCIe alone, which matters when one training job is spread across several GPUs.
SXM modules are mounted directly on a server baseboard rather than slotted in as cards, the layout typically used for dense multi-GPU servers.
TDP is the rated thermal design power: the planning figure for power delivery and cooling in a server.
- Primary use (recorded)
- HPC / legacy AI training
These are the uses Kovara has recorded for this part. The notes explain the workload in general terms; they are not performance claims.
- HPCScientific and engineering simulation, where numerical precision and memory bandwidth matter.
- legacy AI trainingTeaching a model from data. Usually the most compute- and memory-hungry phase, often spread across many GPUs.
Figures are Kovara master data, last verified 03 Sept 2026. Explanations describe the technology in general; they are not benchmarks and say nothing about price or availability.
Explore this accelerator on Compute- HBM2 stacks
- GPU die
- Interposer
- Board
- Power
- Input
- Output
- NVLink
- Neighbouring GPU
- SXM connector
Market Intelligence
Market pricing is not yet tracked for this accelerator.
Tracked coverage does not describe all market supply or geographic availability.
Explore Compute →Technical Specifications
Recorded hardware attributes. Not tracked is distinct from No.
Compute
- Architecture
- Pascal
- Generation
- Pascal
- Primary use
- HPC / legacy AI training
Memory
- VRAM
- 16 GB
- Memory type
- HBM2
- Memory bandwidth
- 0.732 TB/s
Platform
- Form factor
- SXM2
- TDP
- 300 W
- NVLink supported
- Yes
- MIG supported
- No
Lifecycle / usage
- Primary use
- HPC / legacy AI training
- Launch year
- 2016
- Generation status
- Legacy
- Last verified
- 03 Sept 2026
Data & Evidence
Public source evidence is not currently available for Kovara-tracked coverage.