For decades, better chips mostly meant smaller transistors on a single piece of silicon. That approach runs into a hard limit: a lithography scanner can only expose a fixed area, the reticle field, in one shot, so a single die cannot grow beyond it. High-NA EUV scanners, the next generation of lithography tools, halve that field, which makes large single dies harder still. [1]

The largest AI processors have already reached the limit. NVIDIA describes its Blackwell GPUs as two reticle-limited dies, built on a custom TSMC 4NP process and holding 208 billion transistors in total, joined by a 10 TB/s chip-to-chip interconnect so that software sees them as one GPU. From here, much of the growth in AI hardware depends on how well separate dies can be joined, which is the job of advanced packaging. [2]

A chiplet is a die designed to be combined with others in one package rather than to work alone. AMD popularised the approach in server processors: it says its first chiplet product was the second-generation EPYC processor with Zen 2 cores, introduced in 2018. The top Rome EPYC combined eight CPU-core dies made on a 7-nanometre process with a central I/O and memory die made on 14 nanometres, nine chips in all. [3][4]

The logic is economic as well as technical. Small dies yield better than one huge die, because a single defect ruins less silicon. Each function can use the process that suits it; I/O circuits, which must drive signals off the package, gain little from the newest node. And one set of dies can be recombined into many products. The cost is the energy and latency of moving data between dies, which is exactly what better packaging tries to reduce.

In 2.5D packaging, dies sit side by side on a layer that carries far finer wiring than a circuit board. TSMC's CoWoS family is the dominant example for AI. CoWoS-S, in production since 2012, uses a silicon interposer of up to about 3.3 times the reticle, or roughly 2,700 square millimetres. CoWoS-R uses an organic redistribution-layer interposer, and CoWoS-L combines a molded interposer with embedded local silicon bridges, with 3.5-reticle versions in volume production since 2024. [5]

Other approaches avoid a full interposer. Intel's EMIB embeds small silicon bridges in the package substrate only where dies meet, giving high-bandwidth links between large chiplets without a silicon interposer; Intel says its second generation reduced bump pitch from 55 to 45 microns. TSMC's InFO, a fan-out wafer-level technology in high-volume shipment since 2016, uses dense redistribution layers and is widely used for mobile processors, with variants for multi-chiplet designs. [8][6]

HBM is the reason 2.5D packaging matters so much for AI. An HBM4 stack exposes a 2,048-bit interface, and a GPU may have eight stacks. Thousands of short, dense connections of this kind cannot be routed through an ordinary circuit board, so the memory has to sit on the same interposer as the processor. [9]

3D packaging bonds dies directly on top of one another, giving the shortest possible connections. TSMC's SoIC starts at bond pitches below 10 microns, supports chip-on-wafer and wafer-on-wafer stacking, and TSMC says its 3-nanometre chip stacking entered volume production in 2025. Intel's Foveros Direct attaches chiplets to an active base tile with copper bonding at a 9-micron pitch in its first generation, and Intel combines Foveros with EMIB in what it calls EMIB 3.5D. [7][8]

AMD's Instinct MI300 series shows how the two approaches combine. Its GPU compute dies are stacked on top of four I/O dies, which sit on a silicon interposer on TSMC's CoWoS alongside the HBM3 stacks; AMD described the result as a mix of 2.5D and 3.5D packaging. The MI300X contains 153 billion transistors on TSMC's 5 nm and 6 nm processes. [10][11]

Counting the parts of one MI300X makes the idea concrete: eight GPU compute dies, four I/O dies and eight HBM3 stacks, 20 dies in all according to TechInsights, before counting the individual DRAM layers inside each stack. Each HBM stack is itself a 3D structure of DRAM dies linked by through-silicon vias. [12]

Most chiplet designs so far use proprietary links between dies from the same company. Universal Chiplet Interconnect Express aims to standardise that interface so dies from different vendors can be mixed. The UCIe consortium launched in March 2022 with semiconductor, packaging, IP, foundry and cloud companies, was incorporated that August, released version 2.0 with support for 3D packaging in August 2024, and published version 3.0 with data rates of up to 64 GT/s in August 2025. [13]

Whether an open market for chiplets develops is still an open question. The largest AI chips remain vertically integrated designs whose dies come from one vendor, and the practical benefit of UCIe so far is mainly a shared toolkit for building multi-die products rather than off-the-shelf interchangeability.

Because every HBM-based accelerator has to pass through 2.5D packaging, the number of AI GPUs that can be shipped is capped by interposer and assembly capacity as well as by wafer supply. On its October 2025 earnings call, TSMC chief executive C.C. Wei said both front-end and back-end capacity were very tight, that advanced packaging now accounted for slightly over 10 percent of TSMC's revenue, and that TSMC planned two advanced packaging fabs in Arizona while an assembly partner built capacity there too. [14]

Packaging is also drawing memory makers and foundries closer. SK hynix agreed in 2024 to use TSMC's logic process for the HBM4 base die and to optimise how its HBM integrates with CoWoS. The HBM stack, the logic die and the interposer increasingly have to be designed together rather than bought separately. [15]

For people renting or buying GPU capacity, packaging explains why new accelerators arrive in limited volumes and why supply loosens only as interposer and assembly lines expand. It also explains why multi-die products such as B200 and MI300X can carry more memory than their predecessors. Our view is that packaging capacity, alongside HBM, will remain one of the main factors setting how quickly new GPU generations become cheap to rent. On Kovara you can track availability and hourly prices for those generations across providers, compare them side by side, or ask Kova how a given GPU is built.