DDR5, LPDDR5X, GDDR7 and HBM all store bits in the same basic kind of cell: dynamic RAM, a tiny capacitor that has to be refreshed. What separates them is the interface and the physical arrangement. DDR5 sits on removable modules; LPDDR5X is soldered close to the processor; GDDR chips sit on the circuit board around a graphics chip; and HBM stacks dies vertically and places them in the same package as the processor. [1][4][7][11]

Those choices lead to different trade-offs. A narrow interface can run very fast per pin but needs careful signalling over the board. A very wide interface can run slower per pin and still move more data, but only if the wires are short, which in practice means placing memory next to the processor on an interposer. Most of the differences below follow from that tension.

JEDEC published the DDR5 standard, JESD79-5, in July 2020. It started at 4.8 Gb/s per pin, split each module into two independent 40-bit sub-channels, lowered the supply voltage from 1.2 to 1.1 volts, and moved voltage regulation onto the module. A 2024 revision extended defined speeds to 8,800 MT/s. [1][2]

DDR5's strength is capacity. AMD's EPYC 9005 server processors support up to 12 channels of DDR5-6400 and up to 6 TB of memory per socket. That is far more than any GPU can hold, but the bandwidth is modest by accelerator standards. [3]

LPDDR was designed for phones and laptops. JEDEC's LPDDR5X update, published in July 2021, raised the data rate to 8,533 MT/s, a third faster than LPDDR5, and added features such as per-pin equalisation to keep signals clean at higher speeds. [4]

NVIDIA brought LPDDR5X into the data center with its Grace CPU. A single Grace CPU can carry up to 480 GB of LPDDR5X, with bandwidth of up to 512 GB/s depending on the configuration, and NVIDIA says its memory subsystem delivers up to about 500 GB/s in roughly 16 watts, around a fifth of the power of conventional DDR5. In the GH200 Grace Hopper Superchip, Grace's LPDDR5X is joined to the Hopper GPU's HBM through a 900 GB/s coherent NVLink-C2C link, so the GPU can reach a large pool of slower memory as well as its own fast HBM. [5][6]

The combination changes how much memory a single node can address quickly. NVIDIA says a GH200 NVL2 configuration, which links two Grace Hopper Superchips, provides up to 288 GB of high-bandwidth memory with 10 TB/s of bandwidth and 1.2 TB of fast memory in total once the LPDDR5X is included. For models or caches that do not fit in HBM alone, that larger second tier can be cheaper than adding more GPUs, although it is far slower than the HBM itself. [6]

Graphics DDR trades capacity for speed per pin. JEDEC published GDDR7 in March 2024, doubling bandwidth over GDDR6 to as much as 192 GB/s per device. It uses three-level PAM3 signalling to carry more data per clock, increases independent channels from two to four, and adds on-die error correction and other reliability features that earlier graphics memory lacked. [7]

NVIDIA's GeForce RTX 5090 shows GDDR7 at the top of the consumer market: 32 GB on a 512-bit bus at 28 Gb/s per pin, for 1.792 TB/s. GDDR also appears in data-center products. The L40S carries 48 GB of GDDR6 at 864 GB/s, and NVIDIA's Rubin CPX, announced in September 2025 for availability at the end of 2026, pairs 128 GB of GDDR7 with compute designed for the context-processing phase of long-prompt inference. [8][9][10]

HBM takes the opposite approach to GDDR. Each stack exposes 1,024 data pins in HBM3, running at up to 6.4 Gb/s for 819 GB/s per stack, and HBM4 doubles the interface to 2,048 bits for up to 2 TB/s per stack and as much as 64 GB. Because thousands of wires cannot be routed across an ordinary circuit board, the stacks sit in the same package as the processor. [11][12]

Placing several stacks around a GPU produces bandwidth no other DRAM type matches. NVIDIA's H200 has 141 GB of HBM3e at 4.8 TB/s, and each Rubin GPU in a Vera Rubin NVL72 system carries 288 GB of HBM4 at 19.2 TB/s. [13][14]

Memory power is becoming a design constraint in its own right, and vendors now market efficiency alongside speed. Samsung says its HBM4 is about 40 percent more power-efficient than its HBM3E, and NVIDIA's Grace figures show LPDDR5X using around a fifth of the power of DDR5 for similar bandwidth. [15][5]

Cost runs the other way. Micron said at Hot Chips in August 2026 that HBM needs roughly three times the wafer area of DDR5 for the same capacity, because of its many banks, wide data paths, power delivery and through-silicon vias, and that the gap is widening. HBM then has to be assembled with the processor on an interposer. First-generation HBM showed the commercial risk early: AMD's Radeon R9 Fury X of 2015 offered 512 GB/s from four stacks but held only 4 GB. [16][17]

A rough map of the market: DDR5 for general-purpose servers and PCs that need large, expandable capacity; LPDDR5X for phones, laptops and power-sensitive server CPUs such as Grace; GDDR6 and GDDR7 for gaming GPUs, workstation cards and some inference accelerators where cost per unit of bandwidth matters; and HBM for training and large-model inference accelerators such as the H100, H200, B200 and MI300X, where bandwidth per chip is the priority. Heterogeneous designs increasingly combine them, as GH200 does with LPDDR5X and HBM.

For GPU renters, memory type is a quick filter. GDDR cards such as the L40S or RTX-class GPUs are often the cheapest option for small models, image generation and batch jobs that fit in 24 to 48 GB. HBM GPUs cost more per hour but are usually the only practical choice once a model's weights and its KV cache outgrow that, or when token throughput depends on bandwidth. On Kovara you can filter GPUs by memory type and capacity, compare hourly prices across providers, or ask Kova whether a GDDR card will be enough for your workload.