Every leading AI accelerator is now surrounded by stacks of High Bandwidth Memory, and the amount per chip keeps rising. NVIDIA's Rubin GPU carries 288 GB of HBM4, and AMD has previewed an MI400 series with up to 432 GB. When demand for accelerators rises, demand for HBM rises with it and in larger proportion, because each new generation packs in more gigabytes per GPU. [1][2]

HBM is also expensive to make in terms of silicon. At Hot Chips in August 2026, Micron said HBM needs about three times the wafer area of DDR5 for the same capacity, and that the gap widens with each generation. The reasons are structural: an HBM4 die has 256 banks against 32 on a DDR5 die, and it needs extra area for data paths, power delivery and the through-silicon vias that link each layer to the base die. Every wafer diverted to HBM therefore removes a larger amount of conventional DRAM from the market. [3]

Suppliers have described the result plainly. In December 2025 Micron said it had already agreed pricing and volumes for its entire calendar 2026 HBM supply, including HBM4, and that it could meet only around half to two-thirds of demand from core customers. Samsung, announcing HBM4 shipments in February 2026, forecast that its HBM sales would more than triple in 2026 compared with 2025. [4][5]

SK hynix's lead has deep roots. It worked with AMD on HBM from 2010, and it describes itself as the only company that has developed and supplied every generation from the first HBM to HBM3E. According to reporting by Korea JoongAng Daily, Samsung at one point judged HBM too complex and too niche to prioritise, a decision that left SK hynix better placed when AI demand took off. [7][8]

The company delivered the first eight-layer HBM3E to customers in March 2024 and began mass-producing 12-layer HBM3E in September 2024, using its MR-MUF stacking process and dies thinned by 40 percent. In September 2025 it said it had completed HBM4 development and prepared mass production, with per-pin speeds above 10 Gb/s and power efficiency more than 40 percent better than before. It has also partnered with TSMC to use TSMC's logic process for the HBM4 base die and to optimise the fit between its HBM and TSMC's CoWoS packaging. [8][9][10]

Samsung led the overall DRAM market in the second quarter of 2026, according to Counterpoint Research, but it struggled in the HBM3E cycle. The Korea Economic Daily reported in September 2025 that Samsung had only then passed NVIDIA's qualification for 12-layer HBM3E, after roughly 18 months of effort and a redesign of the DRAM core to fix thermal issues, making it the third approved supplier after SK hynix and Micron. Samsung had already been shipping 12-layer HBM3E to AMD, whose MI350 series uses memory from Samsung and Micron. [21][11][2]

Samsung took a more aggressive approach with HBM4. It built the stack on its sixth-generation 10-nanometre-class DRAM process and a 4-nanometre logic base die from its own foundry, and in February 2026 announced commercial shipments running at a consistent 11.7 Gb/s per pin, well above the 8 Gb/s JEDEC baseline. In May 2026 it began shipping HBM4E samples rated at 14 Gb/s per pin and up to 3.6 TB/s per stack. [5][6]

Micron entered the high end of the market with HBM3E. In February 2024 it announced volume production of an eight-high, 24 GB stack running above 9.2 Gb/s per pin, and said the part would ship in NVIDIA's H200. Its HBM3E is also used in AMD's MI350 series. [12][2]

In its fiscal third-quarter results on 24 June 2026, Micron reported revenue of 41.46 billion dollars and said its HBM4, built on its 1-beta DRAM process, was in high-volume shipments for a lead customer's platform, with HBM4E on its 1-gamma process expected to reach volume production in calendar 2027. The company is scheduled to report fiscal fourth-quarter results on 30 September 2026, so figures in this section may soon be superseded. [13][14]

Market-share figures for HBM come from research firms rather than the companies, and estimates differ. As reported by Korea JoongAng Daily, Counterpoint Research estimated that SK hynix held 50 percent of HBM revenue in the second quarter of 2026, Samsung 33 percent and Micron 18 percent. In the first quarter the split had been 58, 21 and 21 percent, and Counterpoint attributed Samsung's gain to its ramp of HBM4 shipments. [15]

The shift matters for GPU supply more than for any single vendor. With three qualified suppliers of HBM4 rather than one or two, accelerator makers have more room to secure volume, and a late or low-yielding supplier is less likely to hold back a whole product generation. Still, the ranking is volatile and depends heavily on which supplier is qualified for which NVIDIA and AMD platform at a given moment.

All three companies are spending heavily. TrendForce reported in March 2026 that SK hynix approved about 21.6 trillion won of additional investment in its Yongin site through 2030 and pulled the first cleanroom forward to February 2027; that Samsung is combining memory and logic foundry in new phases at Pyeongtaek; and that Micron is building fabs in New York and Idaho. Micron raised its fiscal 2026 capital spending plan to about 20 billion dollars and reported 19.6 billion dollars of capex in the first nine months of the year. [16][4][13]

Back-end capacity is growing too. Micron broke ground on an HBM advanced packaging plant in Singapore, an investment of about 7 billion dollars, with operations due to start in 2026 and a meaningful capacity increase from 2027. SK hynix plans an HBM advanced packaging and research facility in West Lafayette, Indiana, worth about 3.87 billion dollars and backed by up to 458 million dollars of US CHIPS Act funding, with mass production projected for the second half of 2028. [17][18]

An HBM stack is useless until it is mounted next to a processor. For most AI accelerators this happens on TSMC's CoWoS platform, which places the logic die and HBM stacks on an interposer; TSMC's silicon-interposer version, CoWoS-S, supports interposers of up to about 3.3 times the lithography reticle, and its CoWoS-L variant has been in volume production since 2024. Memory supply and packaging supply are therefore linked: extra HBM does not become extra GPUs unless interposer capacity grows at the same time. [19]

TSMC has acknowledged the strain. On its October 2025 earnings call, chief executive C.C. Wei said both front-end and back-end capacity were very tight and that advanced packaging had grown to slightly over 10 percent of revenue. HBM4 also deepens the link between memory makers and logic foundries, because the base die of the stack is increasingly built on a logic process: SK hynix uses TSMC, while Samsung uses its own foundry. [20][10][5]

For buyers of GPU time, HBM supply is one of the main reasons new accelerator generations arrive slowly and cost more at first. Our reading is that the first year of any new platform will be memory-constrained, and that prices for the newest HBM3E and HBM4 systems will stay firmer than those for older H100 and A100 capacity. On Kovara you can watch how that plays out in live hourly prices, compare providers for the same GPU, or ask Kova which generation offers the most memory per dollar for your workload.