Silicon is the second most abundant element in the Earth’s crust after oxygen, making up about a quarter of it by mass, and ordinary sand, particularly quartz, is rich in silicon dioxide. Turning that raw material into something a chip can be built on requires extreme purification. Intel describes electronic-grade silicon as pure to nine nines, 99.9999999 percent, which works out to roughly one foreign atom for every billion silicon atoms. [1]

Wafer makers start from polysilicon whose metallic impurities have been reduced to a few parts per billion. In the Czochralski (CZ) process used by suppliers such as SUMCO, the polysilicon is melted in a quartz crucible at around 1,420°C. Small, controlled amounts of boron or phosphorus are added to set the electrical resistance, and a seed crystal is dipped into the melt and slowly drawn upwards while rotating. The result is a cylindrical ingot that is a single, continuous crystal. Intel has cited a typical ingot mass of about 100 kilograms. [2][1]

The ingot is ground to a uniform diameter and cut into slices about 1 mm thick with an inner-diameter saw or a wire saw. The slices are then lapped with an abrasive to the target thickness and made parallel, chemically etched to remove the damage left by sawing, and polished with colloidal silica to a mirror finish. Only after cleaning and inspection is the wafer ready to go to a chip factory. [2]

Wafer size has grown over the decades. Early chipmaking used wafers about two inches across; the leading-edge industry standard today is 300 mm, or 12 inches. A larger wafer spreads the cost of each processing step over more chips. Depending on the design, a single 300 mm wafer can hold thousands of small chips or only a few dozen very large ones. [1][3]

Everything that follows happens in a cleanroom. ASML notes that the cleanest ISO class 1 rooms permit no more than 10 particles of 100 to 200 nm per cubic metre of air and none larger than 200 nm; a hospital, by comparison, may contain around 10,000 dust particles per cubic metre. A single particle landing on a wafer at the wrong moment can ruin the transistors beneath it. [4]

A chip is built up in layers, and each layer is made by repeating a similar sequence. First, a thin film of conducting, insulating or semiconducting material is deposited on the wafer. Equipment makers use several techniques for this: chemical vapour deposition (CVD) for thin barriers and tungsten contacts, plasma-enhanced CVD for protective insulating layers, and atomic layer deposition (ALD), which adds material only a few atomic layers at a time for the most critical films. [3][5]

Next the wafer is coated with photoresist, a light-sensitive polymer. With the more common positive resist, the areas hit by ultraviolet light become more soluble; negative resist hardens where it is exposed. The wafer then goes into a lithography scanner, which shines deep ultraviolet (DUV) or extreme ultraviolet (EUV) light, with wavelengths from 365 nm down to 13.5 nm, through a patterned mask called a reticle. The optics shrink the image, typically by about four times, and project it onto the resist. [3][1]

After exposure, the resist is developed and washed away where it has been weakened, leaving a stencil. Etching then removes the underlying material wherever the stencil leaves it unprotected: dry etching uses reactive gases and plasma, while wet etching uses chemical baths. For features smaller than a single exposure can print, fabs combine lithography, deposition and etch in double, quadruple and spacer-based patterning schemes. [3]

A leading-edge chip can have up to around 100 layers, and each must line up with the ones beneath it to within nanometres. Lithography is usually the step that sets the smallest feature size, which is why fabs reserve their most expensive EUV scanners for the most critical layers and use DUV tools for layers with larger features. [4]

Pure silicon is a poor conductor. To build transistors, fabs change its electrical properties in precise regions by ion implantation: the wafer is bombarded with charged atoms of dopant elements, which alters how easily current can flow there. This is what allows switches to be formed and controlled. Once implantation is done, the remaining protective resist is stripped off. [3][1]

Modern transistors also depend on exotic materials. Intel’s illustrated process guide shows a high-k dielectric, laid down in atomic layers, being added under the transistor gate to reduce electrical leakage, a change the industry made as gates became too thin for conventional silicon dioxide. [1]

Above the transistors sits a stack of metal interconnect layers that connect billions of devices into circuits. The copper wiring is typically laid down by electrochemical deposition, essentially electroplating copper ions onto the wafer, and further insulating layers and metal levels are built on top. Intel notes that a chip can carry more than 30 metal layers, forming a three-dimensional web of wires far more complex than the transistor layer itself. [5][1]

When the wafer leaves the fab, each die on it is probed electrically in a step known as wafer sort, and dies that fail are marked. The wafer is then cut with a diamond saw into individual dies. Good dies are mounted on a substrate that carries signals and power to the circuit board, and are usually topped with a heat spreader to move heat away. A final round of testing measures properties such as power draw and maximum clock frequency before chips are sorted and shipped. [3][1]

Packaging has become far more sophisticated for AI hardware. TSMC’s CoWoS technology places logic dies and stacks of high-bandwidth memory side by side on a silicon or redistribution-layer interposer. TSMC says CoWoS has been in volume production since 2012 and that demand rose sharply after generative AI took off in late 2022; its CoWoS-L variant, at 3.5 times the size of a single lithography exposure field, entered volume production in 2024. [6]

Because the patterning loop is repeated for every layer, a wafer passes through hundreds of process steps. ASML puts the time from design to production at more than three months, and up to four months from design to mass production. That long cycle is one reason chip supply reacts slowly when demand jumps. [3][4]

The cost of the factories themselves has risen faster than the industry’s revenue. A 2020 report by Georgetown’s Center for Security and Emerging Technology (CSET) estimated that the cost of leading-edge fabs had grown by about 11 percent a year, compared with about 7 percent a year for the semiconductor market. The same analysis estimated a foundry sale price of roughly $17,000 per 300 mm wafer at the 5 nm node in 2020, against about $9,300 at 7 nm. [7]

Individual tools explain part of the bill. A single High-NA EUV lithography scanner from ASML has been reported to cost up to about $400 million, and a leading fab needs many scanners alongside hundreds of deposition, etch, inspection and metrology tools. Scale explains the rest: in July 2026 TSMC announced a further $100 billion for Arizona, bringing its planned investment in the state to $265 billion for ten fabs, two advanced packaging facilities and an R&D centre. [8][9]

Every GPU hour sold in the cloud traces back to this process. Months-long manufacturing cycles, scarce EUV and advanced-packaging capacity and very expensive wafers all shape how quickly new accelerators reach data centres and what they cost when they arrive. When supply of a new GPU is tight, rental prices tend to stay high until fabs and packaging lines catch up. On Kovara you can compare current GPU cloud prices across providers, look up the specifications of a specific accelerator, or ask Kova how manufacturing constraints are showing up in today’s market.