In the 1940s electronic amplification and switching relied on vacuum tubes, and Bell Labs was among the laboratories looking for a solid-state alternative. In early 1945 William Shockley organised a solid-state physics group there, and in April of that year he sketched the idea of a field-effect amplifier, in which an electric field applied to a semiconductor would control the current flowing through it. [1]

Shockley’s field-effect concept did not work in practice at the time. Electrons trapped at the semiconductor surface, the so-called surface states, blocked the applied field from reaching the material inside. The group’s theorist, John Bardeen, and its experimentalist, Walter Brattain, went on to build a different kind of device altogether. [1][5]

On 16 December 1947 Bardeen and Brattain got their first working semiconductor amplifier. The device pressed two closely spaced gold contacts, held on a plastic wedge, against a slab of high-purity germanium. A voltage on one contact modulated the current through the other, and input signals were amplified by up to 100 times. The device was shown to Bell Labs officials on 23 December, and Shockley later called it a magnificent Christmas present. [1]

Bell Labs announced the invention at a press conference in New York on 30 June 1948. The name “transistor” was proposed by the engineer John Pierce. The company went on to manufacture thousands of the devices in a metal cartridge as the Type A transistor. [1]

The point-contact transistor proved the principle but was delicate and difficult to reproduce. Its importance was nonetheless recognised quickly: in 1956 Shockley, Bardeen and Brattain shared the Nobel Prize in Physics for their research on semiconductors and their discovery of the transistor effect. [2]

Shockley, meanwhile, pursued a different design. On 23 January 1948 he conceived the junction transistor, a sandwich of three layers of doped semiconductor separated by p-n junctions. His key insight was that charge carriers could be injected through the bulk of the germanium rather than only along its surface. A patent application followed in June 1948 and the theory was published in July 1949. This minority-carrier injection principle became the basis of the bipolar transistor. [3]

Turning the theory into hardware required better materials. Bell Labs chemist Gordon Teal built equipment to pull large, pure single crystals of germanium using a technique first described by Jan Czochralski in 1917. From April 1950 Teal and Morgan Sparks added impurity pellets during crystal growth to form n-p-n junctions, and on 4 July 1951 Bell Labs announced grown-junction transistors that outperformed point-contact devices. [4]

Crystal growing is an easy step to overlook, but it is the origin of the single-crystal silicon ingots from which every modern wafer is sliced. The transistor’s history is as much a story of materials and manufacturing as of device physics.

The field-effect idea returned a decade later. In 1959 John Atalla and Dawon Kahng at Bell Labs built the first successful insulated-gate field-effect transistor. They overcame the surface-state problem by growing a thin layer of silicon dioxide on silicon, which passivated the surface and let a metal gate electrode control the channel underneath. The result was the metal-oxide-semiconductor field-effect transistor, or MOSFET. [5]

Development moved quickly. RCA and Fairchild built MOS devices in 1960, Kahng pointed out their potential for integrated circuits in a 1961 memo, RCA demonstrated an experimental 16-transistor MOS chip in 1962, and commercial MOS parts appeared in 1964. The Computer History Museum notes that more than 99 per cent of modern microchips use MOS transistors, because they can be made smaller and consume less power than bipolar devices. [5]

Two further steps made MOS the dominant technology. Frank Wanlass devised complementary MOS, or CMOS, a circuit style pairing n-type and p-type transistors that draws very little power when idle. In 1968 Fairchild introduced the first commercial silicon-gate IC, replacing aluminium gates with polycrystalline silicon to give three to five times the speed in half the chip area; within five years silicon gates had become the industry standard. [6][7]

In 1974 Robert Dennard of IBM and colleagues published rules for shrinking MOS transistors: reduce the dimensions and voltages by a common factor and the transistor becomes faster while its power density stays constant. This gave a physical basis for Gordon Moore’s observation that component counts were doubling at a steady pace, and it guided the industry for decades. [8]

The results were dramatic. Intel’s 4004 microprocessor of 1971 contained 2,300 transistors. By the mid-2000s, however, the gate insulator had become so thin that current tunnelled straight through it. Intel reported that its silicon dioxide gate layer had shrunk to 1.2 nanometres, and the resulting leakage wasted energy as heat. [9][10]

Intel’s answer, announced in January 2007 for its 45-nanometre process, was to replace silicon dioxide with a hafnium-based high-k dielectric and the polysilicon gate with new metal electrodes. The company said the change cut gate leakage by more than ten times. Gordon Moore described it as the biggest change in transistor technology since polysilicon gates arrived in the late 1960s. [10]

A planar transistor controls its channel only from the top, and as channels shortened, the gate lost its grip: current leaked even when the transistor was switched off. In the mid-1990s the US Defense Advanced Research Projects Agency funded a programme to find devices that could scale far below 100 nanometres. A University of California, Berkeley team led by Chenming Hu, Tsu-Jae King Liu and Jeffrey Bokor won a grant and in 1999 reported the FinFET, in which the channel is a thin vertical fin wrapped by the gate on several sides. [11][12]

The industry did not need the idea immediately, and it took about a decade to reach production. On 4 May 2011 Intel announced its 22-nanometre Tri-Gate transistor, its name for a fin-based design in which the gate wraps the fin on three sides. Intel claimed up to 37 per cent higher performance at low voltage than its 32-nanometre planar transistors, or under half the power at the same performance, and first used it in its Ivy Bridge processors. [13][11]

Hu offered a simple analogy for the design: pinching a vein from both sides stops bleeding far more effectively than pressing on it from one side. Wrapping the gate around a fin gives it the same extra grip on the current. [12]

The logical next step is to surround the channel on all four sides. In a gate-all-around transistor the channel is split into stacked horizontal sheets or ribbons, each fully enclosed by the gate. Samsung was first to production, announcing on 30 June 2022 that it had begun making 3-nanometre chips with its Multi-Bridge-Channel FET design, which uses relatively wide nanosheets. Samsung claimed up to 45 per cent lower power, 23 per cent higher performance and 16 per cent less area than its 5-nanometre process. [14]

TSMC moved to nanosheets with its N2 process. The company states that N2, its first-generation nanosheet technology, entered volume production in the fourth quarter of 2025. Intel’s 18A process pairs its RibbonFET gate-all-around transistor, which it describes as its first new transistor architecture in over a decade, with PowerVia, a system that delivers power from the back of the wafer. Intel said the first 18A Panther Lake processors would ship before the end of 2025, with broad availability from January 2026. [15][16]

Each of these transitions, from planar to fin to sheet, addressed the same underlying problem that Shockley faced in 1945: how to make a gate’s electric field control a channel reliably. The geometry has become far more elaborate, but the job has not changed.

Modern accelerators show how far the transistor has come. NVIDIA’s Blackwell GPU, announced in March 2024, contains 208 billion transistors split across two dies built on a custom TSMC 4NP process and joined by a 10 terabyte-per-second chip-to-chip link. That is roughly 90 million times the transistor count of the 4004. [17][9]

For buyers of GPU capacity, transistor history is not merely background. Each new process node and transistor structure changes how much compute a data-center GPU delivers per watt, which in turn shapes rental prices, power budgets and how quickly older generations lose value. When a newer GPU reaches the cloud, it is worth checking whether its price premium matches its efficiency gain. On Kovara you can compare hourly prices across providers for each generation, look up a GPU’s specifications, or ask Kova which card fits a given workload and budget.