On 19 April 1965 Electronics magazine published an article by Gordon Moore, then director of research and development at Fairchild Semiconductor, titled Cramming more components onto integrated circuits. Moore projected that the maximum number of components on a chip would double every year, reaching about 65,000 by 1975. [1][2]

The argument was economic rather than purely technical. Moore’s reasoning was that unit cost falls as the number of components per circuit rises, so manufacturers had a strong financial incentive to keep packing more onto each chip. The projection described where that incentive, combined with steady process improvement, was likely to lead. [2]

This framing is worth remembering because the popular version of Moore’s law, that computers get twice as fast every year or two, is not what he wrote. His subject was how many components could be put on a chip at minimum cost.

By 1975 Moore was at Intel, which he had co-founded. At the IEEE International Electron Devices Meeting that year he showed that his projection had held, and broke the growth into three parts: larger chips, finer line widths and what he called circuit and device cleverness. He estimated that finer dimensions had contributed roughly a 32-fold density gain since 1961, as line widths fell from about 25 micrometres to about 5, while cleverer circuit and device design had contributed about 100-fold. [3][1]

Moore expected the cleverness factor to run out: he estimated that it had at most about a further fourfold gain to offer. He therefore predicted that the pace would slow to a doubling every two years by the end of the 1970s. Intel summarises the revised statement as a doubling of transistors every two years with minimal rise in cost. [3][4]

The phrase Moore’s law was coined by the Caltech professor Carver Mead. Intel itself stresses that it is not a scientific law but a projection that has required continual innovation to sustain. Moore died on 24 March 2023. [2][4]

For decades the projection proved remarkably accurate, partly because the industry used it as a target and organised its roadmaps around it. The Intel 4004 microprocessor of 1971 had 2,300 transistors. By 1995 Intel’s Pentium held nearly 5 million, and Moore said the trend would continue past a billion. [5][1]

Data-center GPUs show where the curve has gone since. NVIDIA’s H100, announced in 2022, contains 80 billion transistors on a single die of 814 square millimetres. Its successor, Blackwell, announced in 2024, reaches 208 billion transistors, but only by joining two dies in one package. [11][12]

Moore’s law described transistor counts. What made each generation faster as well as denser was a separate principle. In 1974 Robert Dennard of IBM and colleagues showed that if a transistor’s dimensions and voltages were reduced together, it would switch faster while its power density stayed constant. That scaling rule gave Moore’s projection a scientific foundation. [6]

John Hennessy and David Patterson, in their Turing Award lecture, published in Communications of the ACM, date the breakdown of Dennard scaling to around 2007, and describe it as having faded to almost nothing by 2012. Once transistors could no longer be made faster without raising power density, designers turned to multiple cores and, eventually, specialised hardware. The same authors estimated that by 2018 actual transistor density was about 15 times below where Moore’s original projection would have put it. [7]

Hennessy and Patterson argue that the way forward lies in domain-specific architectures, hardware designed around a narrower class of workloads such as neural networks. GPUs with dedicated matrix units are a prominent example of that shift. [7]

Arguments over whether Moore’s law is dead often talk past each other, because people mean different things by it. If it means transistor counts on the most advanced chips keep rising, the trend continues. If it means the cost per transistor, or per unit of performance, keeps falling at the old pace, the evidence is much weaker.

Industry leaders have taken both sides. In September 2022, when asked about the pricing of new GeForce cards, NVIDIA chief executive Jensen Huang said Moore’s law was dead, arguing that getting twice the performance at the same cost every year and a half was over and that leading-edge wafers had become far more expensive. In December 2023 Intel’s then chief executive Pat Gelsinger said the pace had slowed to roughly a three-year doubling but that it was not finished, citing new transistor structures, backside power delivery and 3D stacking. [8][9]

Intel has set a goal of 1 trillion transistors on a package by 2030, an aim that depends on combining several dies rather than on one piece of silicon. Gelsinger also noted that the cost of a leading-edge fab had roughly doubled to about 20 billion dollars within seven or eight years, a reminder that the economics Moore described in 1965 now work against the industry. [4][9]

AI training and inference expose the limits of a single chip. A lithography tool can only print a die up to a maximum area, the reticle limit, so the largest accelerators now combine several dies. TSMC’s CoWoS packaging places logic chiplets and stacks of high-bandwidth memory side by side on a shared interposer; TSMC says its CoWoS-S interposers reach about 3.3 times the reticle size, and a CoWoS-L variant at 3.5 times has been in volume production since 2024. TSMC also notes that demand for CoWoS accelerated from late 2022 with the rise of generative AI. [10]

Memory is the second constraint. Large models must stream enormous amounts of data, and arithmetic units sit idle if memory cannot keep up. The H100 SXM5 was the first GPU with HBM3 memory, offering more than 3 terabytes per second of bandwidth. Blackwell ties two dies together with a 10 terabyte-per-second link so they behave as one GPU. [11][12]

The third lever is parallelism across many chips. NVIDIA’s fifth-generation NVLink provides 1.8 terabytes per second of bidirectional bandwidth per GPU, and its GB200 NVL72 rack connects 72 Blackwell GPUs and 36 Grace CPUs into a single liquid-cooled system. In effect the unit of computing has grown from a chip to a package to a rack. [12]

If transistors no longer get cheaper at the old pace, new accelerators will not automatically make compute cheaper. Gains increasingly arrive as bigger, costlier systems that are more efficient per unit of work but carry high prices per hour. That is why comparing GPU rental prices on cost per useful output, rather than headline hourly rate, matters more than it did a decade ago. On Kovara you can compare prices for the same GPU across providers, check a card’s memory capacity and bandwidth, or ask Kova whether a newer generation is worth its premium for your workload.