For decades, a node’s name described something real. It tracked physical features such as the transistor’s gate length, the distance between its source and drain, or the metal half-pitch, half the spacing from one interconnect wire to the next. Those features typically shrank by about 30 percent with each generation; cutting both the length and width of a circuit by 30 percent halves its area, doubling transistor density. That rhythm underpinned Moore’s Law and gave the industry a simple shorthand for progress. [1]

The link broke in the mid-1990s. Chipmakers began shrinking the transistor gate faster than other features to gain speed, so that what was sold as a 130 nm process had gates of about 70 nm. Later, as power density became the main constraint, engineers improved transistors with strained silicon, new materials and new shapes instead of simply shrinking them. By the time Intel introduced FinFETs at its 22 nm node in 2011, the devices had 26 nm gate lengths, a 40 nm half-pitch and fins 8 nm wide. None of those numbers was 22. [1]

Today the number is best read as a generation label. Industry researchers note that the node number no longer corresponds to gate length, half-pitch or any other single feature on the chip, which is why they have proposed replacing it with direct density measures. Intel’s newer names, such as Intel 3 and Intel 18A, likewise function as labels for successive generations rather than as dimensions. [1][2]

Because names no longer mean much, engineers look at what a process actually delivers. Researchers from Stanford and Berkeley, writing in IEEE Spectrum in 2020, proposed replacing node names with three densities: logic transistors per square millimetre, memory cells per square millimetre and interconnects between logic and memory per square millimetre. At the time, 5 nm-class chips packed roughly 100 million transistors into each square millimetre, and TSMC’s 5 nm SRAM reached about 286 million transistors per square millimetre. [1]

Foundries themselves describe each new node relative to the previous one, in terms of speed at the same power, power at the same speed and density. TSMC, for instance, says its N2 process offers 10 to 15 percent higher performance or 25 to 30 percent lower power than N3E, with about 15 percent higher transistor density. Intel says 18A delivers up to 18 percent more performance at the same power, 38 percent less power at the same performance and 30 percent better density than Intel 3. [7][2]

Each foundry sets its own naming, so a “3nm” process from one company is not guaranteed to match another company’s in density or performance. Samsung, for example, reports its first-generation 3 nm process as offering up to 45 percent lower power, 23 percent more performance and 16 percent smaller area than its own 5 nm process, while its second generation improves those figures to 50, 30 and 35 percent. The comparisons are always with the company’s own earlier nodes, not with competitors. [4]

Variants add another layer. TSMC offers N2, a performance-oriented N2P, a later N2U, and A16, which is essentially N2P with backside power added. A single company can therefore sell several flavours of the same generation, tuned for phones, PCs or data-centre chips. [7][8]

A transistor is a switch: a voltage on the gate turns current on or off in a channel. As transistors shrank, keeping tight control of that channel became harder, and simple shrinking no longer delivered the gains it once had. The industry’s answer in 2011 was the FinFET, introduced by Intel at its 22 nm node, which raised the channel into a thin vertical fin, 8 nm wide in Intel’s first version, so the gate could grip it more effectively. [1]

Gate-all-around (GAA) transistors go further: the channel is fully surrounded by the gate, which Intel says gives precise electrostatic control and better management of short-channel effects than FinFETs. The channels are made as stacked horizontal sheets, often called nanosheets. Samsung was first to production, announcing on 30 June 2022 that it had begun 3 nm manufacturing with its GAA design, which it calls MBCFET. Intel’s version, RibbonFET, is part of Intel 18A, and TSMC began volume production of its first nanosheet process, N2, in the fourth quarter of 2025. [4][2][5]

Gate-all-around gives designers another knob: the width of the nanosheets can be varied, allowing wider sheets for high drive current or narrower ones for lower power. Samsung highlights this flexibility as a way to tune a process for different customers. [4]

On conventional chips, both signal wires and power wires are built above the transistors in the same metal stack, so they compete for space and power must travel down through many layers. Backside power delivery moves the power network to the other side of the wafer. Intel’s PowerVia puts coarse power wiring and bumps on the back of the die and connects them with nanoscale vias; Intel says this reduces worst-case voltage droop by up to ten times. [2]

TSMC’s equivalent, Super Power Rail, is part of its A16 process, which TSMC says improves logic density and is aimed at data-centre products. In April 2026, TSMC said A16 would be ready for production in 2026 but that customer volume production would begin in 2027. [6][8]

Intel launched its Core Ultra Series 3 laptop processors, the first products built on Intel 18A, at CES in January 2026, describing 18A as the most advanced process ever developed and manufactured in the United States. Intel lists 18A as in high-volume production. [3][2]

TSMC’s N2 has been in volume production since late 2025. In its second-quarter 2026 results, TSMC reported that 2 nm accounted for 3 percent of wafer revenue, while 3 nm and 5 nm made up 30 and 33 percent respectively, and it expected a steep ramp of 2 nm in the third quarter. Its roadmap continues with A14 in 2028 and A13 and A12 in 2029. [5][9][8]

For AI accelerators the node matters mostly through efficiency and density: more transistors per die and less energy per operation. But node names are a weak guide when comparing GPUs. The H100 and the Blackwell generation both use TSMC 4-class processes, yet differ greatly in performance because of architecture, packaging and memory. When choosing hardware, it is more useful to compare measured throughput, memory capacity and bandwidth, and the price per hour. Kovara lets you look up individual GPUs, compare their cloud prices across providers, or ask Kova whether a newer node is worth the premium for your workload.