Lithography is the step that prints a chip’s pattern onto a wafer. A scanner projects light through a patterned mask onto a light-sensitive coating, and the smallest feature it can print depends mainly on two things: the wavelength of the light and the numerical aperture (NA) of the optics, a measure of how wide a cone of light the lens can collect. Roughly, the critical dimension equals a process factor k1 multiplied by the wavelength divided by the NA, so a shorter wavelength or a larger NA both allow smaller features. [8]

The industry has moved to ever shorter wavelengths. Mercury-lamp i-line systems at 365 nm pushed features below a micron, krypton fluoride lasers at 248 nm reached about 80 nm, and argon fluoride systems at 193 nm, including immersion versions, eventually printed features of 38 nm. EUV jumps to 13.5 nm, more than 14 times shorter than the 193 nm light it succeeds and close to the X-ray range. [2][1]

Before EUV was ready, chipmakers kept shrinking features with 193 nm light by splitting one layer into several exposures and etch steps, known as double, quadruple and spacer-based patterning. That works, but every extra pass adds time, cost and chances for misalignment. EUV lets many of those layers be printed in one exposure. [5]

There is no simple lamp or laser that emits 13.5 nm light, so ASML generates it from a plasma. Droplets of molten tin about 25 microns across are fired through a vacuum chamber at around 70 metres per second. A low-power laser pulse first flattens each droplet into a pancake shape, and a much more powerful CO2 laser pulse then vaporises it into a plasma that emits EUV light. ASML says this happens up to 50,000 times per second. [2][1]

Because EUV light is absorbed by almost everything, including air and glass, the entire light path runs in a high vacuum and the system uses multilayer mirrors rather than lenses to collect and focus it. The optics come from ZEISS, ASML’s long-standing optics partner. The mask itself is reflective rather than transparent. Meanwhile the wafer stage positions the wafer to within a quarter of a nanometre, correcting its position 20,000 times per second. [1][8]

EUV took decades to industrialise. Researchers in Japan projected the first EUV images in the mid-1980s, and laboratories in the United States and the Netherlands followed in the late 1980s and 1990. An industry coalition began pursuing the technology in the 1990s, but ASML says it was the only company that carried the work through to a commercial system. ASML launched its EUV programme in 1997, formed the EUCLIDES consortium with ZEISS and Oxford Instruments in 1998, and shipped the first prototypes to research centres imec and SUNY in 2006. [3][1]

The first pre-production NXE:3100 system achieved first light at Samsung at the end of 2010, and the first production-grade NXE:3300 shipped in 2013. The first consumer device to use EUV-made chips, according to ASML, was Samsung’s Galaxy Note10 in 2019. ASML shipped its 100th EUV system in December 2020. [3]

ASML’s standard EUV platform, the NXE series, has a numerical aperture of 0.33 and prints features down to 13 nm. The company lists these machines as supporting 7 nm, 5 nm and 3 nm logic nodes as well as leading-edge DRAM. Fabs use EUV for the most critical layers with the smallest features and keep cheaper DUV machines for layers with larger features. [1][6]

EUV did not make advanced chips cheap. Georgetown’s CSET estimated in 2020 that a 5 nm wafer sold for about $17,000, against roughly $9,300 at 7 nm, and attributed part of the gap to the high cost of EUV equipment. The benefit is that far more transistors fit on each wafer, and designs that would have needed many rounds of multi-patterning become practical to manufacture. [12]

ASML’s sole-supplier position has made EUV a matter of national policy. The Dutch government, under pressure from the United States, has not allowed EUV systems to be shipped to China, and ASML has never delivered one there. Restrictions were later extended to some advanced DUV immersion scanners as well. [13]

Since the wavelength is fixed at 13.5 nm, the next lever is the numerical aperture. ASML’s EXE platform raises the NA from 0.33 to 0.55, improving resolution to 8 nm. For the EXE:5200B, ASML claims 40 percent more imaging contrast than NXE systems and transistor densities up to 2.9 times higher, and says the tool is designed for volume production of sub-2 nm logic and leading-edge DRAM. [4][1]

There is a trade-off. Reflective masks limit how steep the light angles can be, so ZEISS and ASML adopted anamorphic optics that magnify differently in two directions. That halves the exposure field from 26 by 33 mm to 26 by 16.5 mm, so very large chips must be stitched together from two exposures and the wafer stages must move faster to keep throughput up. [8]

Intel received the first EXE:5200B in 2025; the tool is rated at 175 wafers per hour, about 60 percent more than the earlier EXE:5000. ASML recognised revenue for two High-NA systems in the fourth quarter of 2025, and in May 2026 its chief executive said the first chips made with High-NA tools were expected within months. Such machines have been reported to cost up to about $400 million each. [9][7][10]

Adoption is split. Intel, Samsung and SK hynix are moving ahead with High-NA plans, while TSMC said in April 2026 that it does not plan to adopt High-NA through 2029, including for its A13 and A12 nodes, arguing that it can keep scaling with existing EUV tools at lower cost. [10][11]

EUV is now central to ASML’s results. The company reported record total net sales of €32.7 billion for 2025, with €7.4 billion of EUV bookings in the fourth quarter alone out of €13.2 billion in total orders. ASML said customers had become more positive about the medium term because of stronger expectations for sustained AI-related demand, and guided for 2026 sales of €34 billion to €39 billion, driven largely by EUV. [7]

Every current flagship AI accelerator depends on EUV-patterned silicon, so the number of EUV scanners in the world is one of the quiet limits on how many GPUs can be built. The divergence over High-NA also matters: if TSMC, which makes most AI accelerators, keeps scaling on standard EUV while rivals adopt High-NA, the cost and timing of future GPU generations will partly reflect that bet. For buyers, the practical effect is that new-generation accelerators arrive at premium prices that ease only as supply grows. You can follow that process on Kovara by comparing GPU cloud prices by model and provider, or ask Kova how pricing for a particular generation has moved.