Semiconductors are among the most traded goods in the world. A 2021 study by the Semiconductor Industry Association (SIA) and Boston Consulting Group (BCG) ranked them as the fourth most traded product category, after crude oil, refined oil and cars. The same study describes a production process of 400 to 1,400 individual steps, with a typical wafer cycle time of around 12 weeks and up to 14 to 20 weeks for some products. [2]

Because each stage demands very different skills and capital, the industry has specialised by stage and by region. SIA and BCG estimate that there are more than 50 points across the chain where one region accounts for 65% or more of global supply. Their 2024 follow-up report repeats this concern about geographic concentration even as new factories are built in more countries. [2][1]

The industry uses a few standard business models. Integrated device manufacturers (IDMs) design, fabricate and package their own chips. Fabless companies only design chips and outsource manufacturing. Foundries fabricate chips for fabless firms and IDMs, spreading the enormous capital cost of a fab across many customers. Outsourced semiconductor assembly and test (OSAT) firms package and test chips under contract. [2]

Every chip begins as a design created with electronic design automation (EDA) software and often built from licensed building blocks known as core IP, such as processor cores or interface circuits. In SIA and BCG's 2024 estimates for 2022, EDA and core IP accounted for about 3% of the industry's value added, while logic chip design accounted for roughly 30%. The 2021 study noted that four of the top five EDA and core IP companies by 2019 revenue were headquartered in the United States. [1][2]

Design is the most research-intensive stage. The 2021 SIA and BCG study attributed about 53% of industry R&D spending to design activities. This is where fabless companies such as GPU and accelerator designers concentrate their engineering, relying on foundries to turn their designs into silicon. [2]

Chip factories depend on highly specialised machines for lithography, deposition, etching, cleaning, inspection and more. In SIA and BCG's 2024 estimates, manufacturing equipment made up about 12% of the industry's value added in 2022, with US firms holding roughly 47% of that segment, Japanese firms around 26% and European firms around 18%. [1]

The most famous chokepoint is extreme ultraviolet (EUV) lithography, which uses light with a 13.5 nm wavelength to pattern the finest features on leading-edge chips. ASML, based in the Netherlands, describes EUV as unique to the company; it shipped its first production EUV system in 2013 after more than 6 billion euros of R&D. SIA and BCG put the cost of a single EUV machine at around 150 million dollars in 2021. [3][2]

Materials are a smaller share of value, about 5% in 2022 by SIA and BCG's estimates, but include items with few suppliers. The 2021 study noted that silicon wafers were supplied mainly by four companies with a combined global share above 90%, and listed specialty gases among the inputs where a single region supplies 65% or more. [1][2]

Front-end fabrication is the capital-heavy core of the chain. SIA and BCG estimated in 2021 that a standard-capacity leading-edge fab costs roughly 5 billion dollars for advanced analog production and up to 20 billion dollars for advanced logic or memory, and that wafer fabrication absorbed about 64% of industry capital expenditure. Their 2024 report projects around 2.3 trillion dollars of private investment in wafer fabrication between 2024 and 2032. [2][1]

The most advanced logic production is the most concentrated. In 2021, SIA and BCG reported that all capacity below 10 nm was located in Taiwan (92%) and South Korea (8%). The 2024 report states that the United States produced no advanced logic chips in 2022, but projects that by 2032 it will hold close to 30% of logic capacity at processes below 10 nm, with more than 40% of such capacity located outside Taiwan and South Korea. It also projects the US share of total global fab capacity rising from 10% to 14%. [2][1]

In the contract manufacturing market, TrendForce estimates that TSMC held 72.5% of top-10 foundry revenue in the second quarter of 2026, followed by Samsung at 5.9%, SMIC at 5.4%, UMC at 3.9% and GlobalFoundries at 3.2%. TSMC's own 2025 annual report says 2 nm production was established in 2025, with further variants planned for volume production in the second half of 2026. The company has also announced plans to raise its planned US investment to 165 billion dollars. [4][5][6]

Memory chips are made by a small group of manufacturers and are geographically concentrated. SIA and BCG's 2024 report shows South Korea holding roughly two-thirds of global DRAM capacity in 2022, with the US share projected to grow from about 3% to 9% by 2032. For NAND flash, the report projects South Korea rising from 30% to 42% of capacity, with Japan and South Korea together accounting for about 75% by 2032. [1]

High-bandwidth memory (HBM), which stacks DRAM dies next to a GPU or accelerator, has become strategically important enough to be regulated directly. In December 2024, the US Commerce Department added export controls on HBM above a memory bandwidth density of 2 gigabytes per second per square millimetre, as described by law firm Holland and Knight. [7]

After fabrication, wafers are cut into dies, packaged and tested. This back-end stage accounted for about 6% of industry value added in 2022 in SIA and BCG's estimates. The 2021 study found that mainland China and Taiwan together held more than 60% of global assembly, packaging and test capacity, and that nine of the ten largest OSAT firms by revenue were headquartered in mainland China, Taiwan or Singapore. [1][2]

For AI accelerators, packaging is no longer a commodity step. Techniques that place a processor and stacks of HBM side by side on a shared substrate, such as TSMC's CoWoS family, are listed in TSMC's annual report alongside its other advanced packaging technologies. The company's 2025 report describes robust AI-related demand throughout the year, and its US expansion plan includes two advanced packaging facilities. [5][6]

The supply chain explains a lot about GPU availability. A data center GPU needs leading-edge foundry capacity, HBM from a handful of memory makers and advanced packaging capacity at the same time, and a shortage at any of those steps limits how many accelerators ship. When those bottlenecks ease or tighten, the effect tends to show up months later in cloud rental prices and in which regions have capacity available.

Kovara tracks the result of these upstream constraints at the point where most buyers meet them: published cloud prices and availability. If you are planning a training run or an inference deployment, compare current GPU prices across providers, look up which regions list the hardware you need, or ask Kova how supply conditions for a specific GPU have been changing.