A wafer is a thin, polished disc of single-crystal silicon on which chips are built. It is sliced from a cylindrical ingot at a thickness of about 1 mm, then lapped, etched and polished to a mirror finish before it enters a fab. [1]

The industry standard for leading-edge logic is a wafer 300 mm, or 12 inches, across. Early chipmaking used wafers only about two inches in diameter. Fabs and foundries often report capacity in 12-inch-equivalent wafers: TSMC, for instance, says the fabs it manages had annual capacity of more than 17 million 12-inch-equivalent wafers in 2025. [2][3]

A die is one copy of a chip design on the wafer. A 300 mm wafer has an area of about 70,700 mm², so dividing by the die area gives a first estimate of how many dies fit. That overestimates the real number, because square dies cannot tile a round wafer: partial dies at the edge are wasted, and space is also lost to the scribe lines between dies and to test structures. A common approximation subtracts an edge-loss term proportional to the wafer circumference divided by the die’s diagonal, and die-per-wafer calculators note that ignoring scribe lines alone can overstate the count by 5 to 10 percent. [4]

Not every die works. Engineers distinguish line yield, the share of wafers that survive the whole fabrication process; die yield, the share of dies on finished wafers that function; and probe yield, measured when each die is tested electrically at the end of fabrication. Die yield is usually the one that matters most for chip economics. [5]

The simplest model treats defects as randomly scattered with an average density D0 per unit area. The probability that a die of area A escapes all of them is then the exponential of minus D0 times A. Real defects tend to cluster, so fabs also use refinements such as the Murphy and negative binomial models, which predict somewhat better yields for large dies than the simple Poisson formula. All the models agree on the main point: with the same process and the same defect density, larger dies have lower yield. [5]

Defect density falls as a process matures, which is why foundries track it closely before volume production. In April 2025 TSMC said the defect density of its N2 process was lower than that of N3, N5 and N7 at the same stage of development, about two quarters before mass production, despite N2 being its first gate-all-around node. [6]

A die with a defect is not always scrap. During testing, chips are measured for how many cores work, which clock speeds they sustain and at what voltage and power. Dies with a faulty core or graphics block can have that section disabled and be sold as a lower-tier product, and dies that run slower or hotter can be sold at lower frequencies. This sorting, called binning, lets manufacturers sell much more of each wafer. Many product families, from desktop CPUs to consumer GPUs, are cut from the same die in this way. [7]

Large AI accelerators are designed with this in mind. NVIDIA’s full GH100 die contains 144 streaming multiprocessors (SMs), but the H100 SXM5 ships with 132 enabled and the H100 PCIe with 114. The full design also has six HBM3 stack positions, of which the shipping products use five. Leaving spare units means a die with a defect in one SM can still be sold. [8]

There is also a hard ceiling on die size. A standard lithography scanner exposes a field of 26 by 33 mm at a time, about 858 mm², and a single die generally cannot be larger than that. High-NA EUV scanners halve the field to 26 by 16.5 mm, which will push the largest designs to stitch patterns across two exposures. [10]

AI chips sit right against that ceiling. The GH100 die in NVIDIA’s H100 measures 814 mm² and holds 80 billion transistors. For its Blackwell generation, NVIDIA went beyond the limit by joining two reticle-limited dies with a 10 TB/s chip-to-chip link so that they behave as one GPU with 208 billion transistors in total. [8][9]

That approach relies on advanced packaging. TSMC’s CoWoS places logic dies and HBM stacks on a large interposer; CoWoS-S supports interposers up to about 3.3 times the reticle size, around 2,700 mm², and CoWoS-L reached 3.5 times the reticle size in volume production in 2024. Splitting a design into smaller dies improves yield, because each piece is less likely to contain a defect, but adds packaging cost and complexity. [11]

Wafers at leading nodes are costly. Georgetown’s CSET estimated in 2020 that a 300 mm wafer at 5 nm sold for about $17,000 and one at 7 nm for about $9,300. In October 2025 TechNode, citing a Chinese industry outlet, reported that TSMC had set 2 nm wafer prices around $30,000, compared with roughly $25,000 to $27,000 at 3 nm. [12][13]

Yield economics help explain why data-centre GPUs cost many times more than consumer chips made on similar processes, and why the first months of a new generation are often the tightest. As defect density falls and packaging capacity grows, more good accelerators come out of each wafer and supply loosens, which eventually shows up in rental prices. On Kovara you can compare what each GPU costs per hour across providers, look up die-level specifications, or ask Kova how supply for a particular accelerator is trending.